114 lines
No EOL
3.1 KiB
Rust
114 lines
No EOL
3.1 KiB
Rust
//! All constants used in the driver, mostly register addresses
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//! Register map: https://arduino.ua/docs/RM-MPU-6000A.pdf
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//! Datasheet with WAY more info about interrupts (Revision 3.2) https://www.cdiweb.com/datasheets/invensense/ps-mpu-6000a.pdf
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//!
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/// Gyro Sensitivity
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pub const GYRO_SENS: (f32, f32, f32, f32) = (131., 65.5, 32.8, 16.4);
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/// Accelerometer Sensitivity
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pub const ACCEL_SENS: (f32, f32, f32, f32) = (16384., 8192., 4096., 2048.);
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/// Temperature Offset
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pub const TEMP_OFFSET: f32 = 36.53;
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/// Temperature Sensitivity
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pub const TEMP_SENSITIVITY: f32 = 340.;
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#[allow(non_camel_case_types)]
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#[derive(Copy, Clone, Debug)]
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/// Register addresses
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pub enum Registers {
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/// Slave address of Mpu6050
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SLAVE_ADDR = 0x68,
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/// Internal register to check slave addr
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WHOAMI = 0x75,
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/// High Byte Register Gyro x orientation
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GYRO_REGX_H = 0x43,
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/// High Byte Register Gyro y orientation
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GYRO_REGY_H = 0x45,
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/// High Byte Register Gyro z orientation
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GYRO_REGZ_H = 0x47,
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/// High Byte Register Calc roll
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ACC_REGX_H = 0x3b,
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/// High Byte Register Calc pitch
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ACC_REGY_H = 0x3d,
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/// High Byte Register Calc yaw
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ACC_REGZ_H = 0x3f,
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/// High Byte Register Temperature
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TEMP_OUT_H = 0x41,
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/// Register to control chip waking from sleep, enabling sensors, default: sleep
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POWER_MGMT_1 = 0x6b,
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/// Internal clock
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POWER_MGMT_2 = 0x6c,
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/// Accelerometer config register
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ACCEL_CONFIG = 0x1c,
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/// gyro config register
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GYRO_CONFIG = 0x1b,
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}
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impl Registers {
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pub fn addr(&self) -> u8 {
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*self as u8
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}
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}
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#[allow(non_camel_case_types)]
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#[derive(Copy, Clone, Debug)]
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pub struct Bits;
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impl Bits {
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/// Accelerometer high pass filter bit: See 4.5 Register 28
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pub const ACCEL_HPF_BIT: u8 = 3;
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/// Gyro Config FS_SEL start bit
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pub const GYRO_CONFIG_FS_SEL_BIT: u8 = 4;
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/// Gyro Config FS_SEL length
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pub const GYRO_CONFIG_FS_SEL_LENGTH: u8 = 3;
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/// Accel Config FS_SEL start bit
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pub const ACCEL_CONFIG_FS_SEL_BIT: u8 = 4;
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/// Accel Config FS_SEL length
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pub const ACCEL_CONFIG_FS_SEL_LENGTH: u8 = 2;
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/// Accel Config FS_SEL start bit
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pub const ACCEL_CONFIG_ACCEL_HPF_BIT: u8 = 2;
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/// Accel Config FS_SEL length
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pub const ACCEL_CONFIG_ACCEL_HPF_LENGTH: u8 = 3;
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}
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#[allow(non_camel_case_types)]
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum ACCEL_HPF {
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_RESET = 0,
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_5 = 1,
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_2P5 = 2,
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_1P25 = 3,
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_0P63 = 4,
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_HOLD = 7
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}
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impl From<u8> for ACCEL_HPF {
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fn from(range: u8) -> Self
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{
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match range {
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0 => ACCEL_HPF::_RESET,
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1 => ACCEL_HPF::_5,
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2 => ACCEL_HPF::_2P5,
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3 => ACCEL_HPF::_1P25,
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4 => ACCEL_HPF::_0P63,
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7 => ACCEL_HPF::_HOLD,
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_ => ACCEL_HPF::_RESET,
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}
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}
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}
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//
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// #[derive(Copy, Clone, Debug)]
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// pub struct BitBlock {
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// reg: u8,
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// start_bit: u8,
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// length: u8
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// }
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//
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// pub const ACONFIG_ACCEL_HBF: BitBlock = BitBlock { reg: Registers::ACCEL_CONFIG.addr(), start_bit: Bits::ACCEL_CONFIG_ACCEL_HBF_BIT, length: Bits::ACCEL_CONFIG_ACCEL_HBF_LENGTH};
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