Switched to DMA
84% load with 1Msps no DMA 2.4% load with 2Msps with DMA
This commit is contained in:
Killorin
parent
bd79be6eac
commit
15a478c9aa
4 changed files with 103 additions and 19 deletions
8
main.c
8
main.c
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@ -188,7 +188,7 @@ void capture_waveform(UArg arg1, UArg arg2)
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int32_t i;
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if (options.fft) {
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adc_current_index = gADCBufferIndex;
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adc_current_index = getADCBufferIndex();
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int32_t j = 0;
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for(i=adc_current_index-FFT_BUF_LEN; i<adc_current_index; i++) {
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adc_buffer_fft_sample[j++] = gADCBuffer[ADC_BUFFER_WRAP(adc_current_index + i)];
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@ -199,7 +199,7 @@ void capture_waveform(UArg arg1, UArg arg2)
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int trigger;
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if (trigger_mode == 2) {
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trigger = gADCBufferIndex - (WIDTH / 2); // show latest if trigger disabled
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trigger = getADCBufferIndex() - (WIDTH / 2); // show latest if trigger disabled
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} else {
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trigger = Trigger(trigger_mode);
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}
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@ -367,7 +367,7 @@ void display_waveform(UArg arg1, UArg arg2)
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int Trigger(bool rising) // search for edge trigger
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{
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int x = gADCBufferIndex - (WIDTH / 2); // half screen width
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int x = getADCBufferIndex() - (WIDTH / 2); // half screen width
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int x_stop = x - ADC_BUFFER_SIZE/2;
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for (; x > x_stop; x--) {
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if (rising) {
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@ -383,6 +383,6 @@ int Trigger(bool rising) // search for edge trigger
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}
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}
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if (x == x_stop) // for loop ran to the end
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x = gADCBufferIndex - (WIDTH / 2); // reset x back to how it was initialized
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x = getADCBufferIndex() - (WIDTH / 2); // reset x back to how it was initialized
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return x;
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}
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6
rtos.cfg
6
rtos.cfg
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@ -36,6 +36,7 @@
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var Clock = xdc.useModule('ti.sysbios.knl.Clock');
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var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox');
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var TimestampProvider = xdc.useModule('ti.sysbios.family.arm.lm4.TimestampProvider');
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var GateHwi = xdc.useModule('ti.sysbios.gates.GateHwi');
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/*
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* Default value is family dependent. For example, Linux systems often only
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* support a minimum period of 10000 us and multiples of 10000 us.
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@ -538,7 +539,7 @@ Clock.timerId = 0;
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TimestampProvider.useClockTimer = true;
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var m3Hwi0Params = new m3Hwi.Params();
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m3Hwi0Params.instance.name = "m3Hwi0";
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m3Hwi0Params.priority = 0;
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m3Hwi0Params.priority = 64;
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Program.global.m3Hwi0 = m3Hwi.create(62, "&ADC_ISR", m3Hwi0Params);
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var task1Params = new Task.Params();
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task1Params.instance.name = "waveform";
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@ -593,3 +594,6 @@ var semaphore4Params = new Semaphore.Params();
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semaphore4Params.instance.name = "options_sem";
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semaphore4Params.mode = Semaphore.Mode_BINARY;
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Program.global.options_sem = Semaphore.create(1, semaphore4Params);
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var gateHwi0Params = new GateHwi.Params();
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gateHwi0Params.instance.name = "gateHwiDMA";
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Program.global.gateHwi0 = GateHwi.create(gateHwi0Params);
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106
sampling.c
106
sampling.c
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@ -7,37 +7,111 @@
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#include "driverlib/sysctl.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/timer.h"
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#include "driverlib/udma.h"
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#include "sysctl_pll.h"
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#include "inc/hw_types.h"
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#include "inc/hw_memmap.h"
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#include <math.h>
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#include "buttons.h"
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#include "sampling.h"
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#include <xdc/std.h>
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#include <xdc/runtime/System.h>
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#include <xdc/cfg/global.h>
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#include <ti/sysbios/gates/GateHwi.h>
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#define DMA
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#ifdef DMA
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#pragma DATA_ALIGN(gDMAControlTable, 1024)
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tDMAControlTable gDMAControlTable[64]; // uDMA control table
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#endif
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extern uint32_t gSystemClock; // [Hz] system clock frequency
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// latest sample index
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void ADC_ISR(void)
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// is DMA occurring in the primary channel?
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volatile bool gDMAPrimary = true;
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void ADC_ISR(void) // DMA
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{
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// clear ADC1 sequence0 interrupt flag in the ADCISC register
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//HWREGBITW(ADC1_ISC_R, 1) = 1;
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ADC1_ISC_R |= 1;
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// check for ADC FIFO overflow
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if(ADC1_OSTAT_R & ADC_OSTAT_OV0) {
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gADCErrors++; // count errors
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ADC1_OSTAT_R = ADC_OSTAT_OV0; // clear overflow condition
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ADCIntClearEx(ADC1_BASE, ADC_INT_DMA_SS0); // clear the ADC1 sequence 0 DMA interrupt flag
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// Check the primary DMA channel for end of transfer, and
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// restart if needed.
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if (uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT) ==
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UDMA_MODE_STOP) {
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// restart the primary channel (same as setup)
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uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT,
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UDMA_MODE_PINGPONG, (void*)&ADC1_SSFIFO0_R,
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(void*)&gADCBuffer[0], ADC_BUFFER_SIZE/2);
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// DMA is currently occurring in the alternate buffer
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gDMAPrimary = false;
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}
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// Check the alternate DMA channel for end of transfer, and
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// restart if needed.
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// Also set the gDMAPrimary global.
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if (uDMAChannelModeGet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT) ==
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UDMA_MODE_STOP) {
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// restart the primary channel (same as setup)
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uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT,
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UDMA_MODE_PINGPONG, (void*)&ADC1_SSFIFO0_R,
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(void*)&gADCBuffer[ADC_BUFFER_SIZE/2],
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ADC_BUFFER_SIZE/2);
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// DMA is currently occurring in the primary buffer
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gDMAPrimary = true;
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}
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// The DMA channel may be disabled if the CPU is paused by the debugger
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if (!uDMAChannelIsEnabled(UDMA_SEC_CHANNEL_ADC10)) {
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// re-enable the DMA channel
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uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC10);
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}
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gADCBufferIndex = ADC_BUFFER_WRAP(gADCBufferIndex + 1);
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// read sample from the ADC1 sequence 0 FIFO
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gADCBuffer[gADCBufferIndex] = (ADC1_SSFIFO0_R & ADC_SSFIFO0_DATA_M);
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}
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int32_t getADCBufferIndex(void)
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{
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int32_t index;
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uint32_t key = GateHwi_enter(gateHwi0);
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if (gDMAPrimary) { // DMA is currently in the primary channel
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index = ADC_BUFFER_SIZE/2 - 1 -
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uDMAChannelSizeGet(UDMA_SEC_CHANNEL_ADC10 |
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UDMA_PRI_SELECT);
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} else { // DMA is currently in the alternate channel
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index = ADC_BUFFER_SIZE - 1 -
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uDMAChannelSizeGet(UDMA_SEC_CHANNEL_ADC10 |
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UDMA_ALT_SELECT);
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}
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GateHwi_leave(gateHwi0, key);
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return index;
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}
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void start_sampler() {
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gADCBufferIndex = ADC_BUFFER_SIZE - 1;
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gADCErrors = 0;
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// init DMA
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SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
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uDMAEnable();
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uDMAControlBaseSet(gDMAControlTable);
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// assign DMA channel 24 to ADC1 sequence 0
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uDMAChannelAssign(UDMA_CH24_ADC1_0);
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uDMAChannelAttributeDisable(UDMA_SEC_CHANNEL_ADC10, UDMA_ATTR_ALL);
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// primary DMA channel = first half of the ADC buffer
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uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT,
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UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
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UDMA_ARB_4);
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uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_PRI_SELECT,
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UDMA_MODE_PINGPONG, (void*)&ADC1_SSFIFO0_R,
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(void*)&gADCBuffer[0], ADC_BUFFER_SIZE/2);
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// alternate DMA channel = second half of the ADC buffer
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uDMAChannelControlSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT,
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UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
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UDMA_ARB_4);
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uDMAChannelTransferSet(UDMA_SEC_CHANNEL_ADC10 | UDMA_ALT_SELECT,
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UDMA_MODE_PINGPONG, (void*)&ADC1_SSFIFO0_R,
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(void*)&gADCBuffer[ADC_BUFFER_SIZE/2],
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ADC_BUFFER_SIZE/2);
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uDMAChannelEnable(UDMA_SEC_CHANNEL_ADC10);
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SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
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GPIOPinTypeADC(GPIO_PORTE_BASE,
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GPIO_PIN_0); // GPIO setup for analog input AIN3
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@ -64,8 +138,12 @@ void start_sampler() {
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ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH3 | ADC_CTL_END | ADC_CTL_IE);
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// enable the sequence. it is now sampling
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ADCSequenceEnable(ADC1_BASE, 0);
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// enable sequence 0 interrupt in the ADC1 peripheral
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ADCIntEnable(ADC1_BASE, 0); // INT_ADC1SS0
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//ADCIntEnable(ADC1_BASE, 0); // INT_ADC1SS0
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ADCSequenceDMAEnable(ADC1_BASE, 0); // enable DMA for ADC1 sequence 0
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ADCIntEnableEx(ADC1_BASE, ADC_INT_DMA_SS0); // enable ADC1 sequence 0 DMA interrupt
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}
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void set_frequency(uint64_t microseconds) {
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@ -17,4 +17,6 @@ void start_sampler(void);
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void set_frequency(uint64_t microseconds);
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int32_t getADCBufferIndex(void);
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#endif /* SAMPLING_H_ */
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